Dynamic CMOS

Laura A. Knauth
EEE 425 Honors Project
Fall 1997
Advisor: ZAck Ciccone

Although static CMOS logic is widely used for its high noise margins and relative ease of design, it is limited at running extremely high clock speeds. For applications requiring the fasted circuit speeds possible, dynamic CMOS logic has numerous advantages over static CMOS including not only higher speeds but also significantly reduced surface area. The advantages do not come without a cost however. Due to the nature of dynamic CMOS logic, undesired effects can occur within the circuit unless extra effort is put into the engineering design. Understanding the basic principles of Dynamic CMOS logic begins with first an understanding of the basic properties of MOSFET devices as well as the characteristics of static and pseudo-NMOS logic.

Due to the internal structure of MOSFET devices, an effective capacitance can be associated across all possible terminal combinations of the gate, drain, source, and body. When charge is applied to these capacitances, the corresponding terminal voltage rises, and when the charge is removed, the terminal voltage decays just as if the terminal were modeled as a capacitor. Modeling the MOSFET terminals as capacitors is useful to explain the voltages and currents associated with the MOSFETs in a complex circuit. MOSFETs are characterized by the three modes of operation: Cutoff, Linear, and Saturated. However, since current flows through the device for both the linear and saturated modes, it is useful to consider the MOSFET as ON in this conducting state or OFF when no current flows. For an NMOS, or n-channeled MOSFET, the device is only ON when the gate to source voltage, VGS, is greater than the device threshold voltage, VT. For a PMOS, or p-channeled MOSFET, the device is only ON when the source to gate voltage, VSG, is greater than the negative device threshold voltage, -VT. For the purposes of this paper, the input to the gates of the MOSFETs will either be high or low, VDD or GND, respectively. Therefore, if the PMOS source is connected to VDD, the PMOS will only be ON if the gate voltage is low. Likewise, if the NMOS source is connected to GND, the NMOS will only be ON when the gate voltage is high. Observing how the NMOS and PMOS work in conjunction to form the CMOS inverter circuit, Fig 1, is a useful example to understand how these devices might be used in more complex circuitry. When the input is low, the PMOS turns ON and the NMOS turns OFF. The output is simultaneously cutoff from GND and charged high due to the ‘pull-up’ path to VDD through the PMOS. Conversely, when the input is high, the PMOS turns OFF and the NMOS turns ON resulting in a ‘pull-down’ path to GND while the connection to VDD is cutoff. When utilized in this fashion, the NMOS device is considered a ‘pull-down’ device, and the PMOS is considered a ‘pull-up’ device.

By connecting the output of this circuit to the input of similar logic, the voltage and current characteristics can be determined by considering the capacitive effects associated with the input of this second stage. As shown in Figure 2, a low input to the CMOS inverter charges the input of the second stage high due to the current from VDD flowing out of the first-stage PMOS. A high input to the inverter removes any charge at the input of the second stage through the NMOS of the first stage.

The capacitive effects of the MOSFET terminals can also be used to store charge across the terminals temporarily. Consider the tristate inverter in Figure 3. When VPEN and VNEN are low (note VPEN is inverted), Vout is disconnected from both VDD and GND leaving Vout floating. In this ‘Z-state,’ Vout must retain its previous voltage level. Ideally, any charge associated with the Z-state would remain across the terminals of the MOSFET indefinitely; however, due to parasitic charge leakage, an originally high voltage in the output Z-state will decay to zero with time. If the system were run at speeds higher than the time needed for the leakage current to cause a logic error, the characteristics of the output Z-state can be utilized to vastly increase circuit speeds. This is the essence of dynamic CMOS.

Although there are many positive reasons for using static CMOS logic, there are also numerous drawbacks. Static devices inherently have more components and clocked transistors than dynamic devices. A full latch for example in the traditional static configuration may require 66 transistors [4]. A dynamic configuration performing the same function may require only 36 transistors [4]. The number of transistors used to construct a flipflop is also significantly reduced by using dynamic logic as opposed to fully static logic. Reducing the total number of transistors not only allows the overall device to be significantly smaller, but also reduces the power requirements of the system.

Most of the disadvantages of using static CMOS, however, are associated with the use of PMOS. Caused in part because hole mobilities are significantly slower than electron mobilities, PMOS devices must be much larger than NMOS devices for the two to have the same ability to transport a fixed amount of charge during a fixed time interval. The larger surface area needed to form a PMOS device than an NMOS device is not only a detriment to the overall chip size, but also increases the capacitance associated to the PMOS device. The larger capacitance and slower carrier mobilities associated with PMOS cause a greater time delay for the PMOS to charge up the capacitor associated with the next logic stage. This increased time delay becomes a bottleneck when trying to design faster circuits. In standard CMOS logic, one PMOS device will always compliment an NMOS device. Altering this logic so that fewer PMOS devices are needed will vastly improve circuit performance.

One method to decrease the number of PMOS devices in the circuit is to use what is called pseudo-NMOS logic. Instead of using one PMOS for every NMOS device, pseudo-NMOS logic utilizes only one PMOS device as a load to all other NMOS logic as shown in Figure 4.

Since the voltage at the gate of the PMOS is always GND, the PMOS device is always ON. The output then of the pseudo-NMOS circuit is selectively discharged to GND through the NMOS logic block. Since the NMOS devices in the ON state forms a pull-down path to GND and the PMOS device is always ON, there will be times during circuit operation where a path is formed from VDD to GND. The pseudo-NMOS logic must be ratio sensitive so as to minimize the loss in power dissipation. In other words, the PMOS must be ‘weak’ or small so as to have less capacitance associated with the device. In this configuration, the charge will be pulled up much more slowly by the PMOS than it can be discharged through the NMOS devices. In this way, a pull-down path to ground through the NMOS logic block should easily pull down the output. When no pull-down path to ground exists via the NMOS logic, the output is then pulled high through the PMOS load. Although pseudo-NMOS logic can be utilized to reduce the number of PMOS components in the system, not only does the static power dissipation serve as a detriment, but the speed of the circuit is limited by the time necessary for the weak PMOS to charge up the output node.

An alternative logic that reduces the number of PMOS devices while also solving most of the problems associated with pseudo-NMOS logic is dynamic CMOS. The basic structure of dynamic CMOS logic is shown in Figure 5. When the clock is low, the NMOS device is cutoff while the PMOS is turned ON. This has the effect of disconnecting the output node from ground while simultaneously connecting the node to VDD. Since the input to the next stage is charged up through the PMOS transistor when the clock is low, this phase of the clock is known as the ‘precharge’ phase. When the clock is high however, the PMOS is cutoff and the bottom NMOS is turned ON, thereby disconnecting the output node from VDD and providing a possible pull-down path to ground through the bottom NMOS transistor. This part of the clock cycle is known as the ‘evaluation’ phase, and so the bottom NMOS is called the ‘evaluation NMOS.’ When the clock is in the evaluation phase, the output node will either be maintained at its previous logic level or discharged to GND. In other words, the output node may be selectively discharged through the NMOS logic structure depending upon whether or not a path to GND is formed due to inputs of the NMOS logic block. If a path to ground is not formed during the evaluation phase, the output node will maintain its previous voltage level since no path exists from the output to VDD or GND for the charge to flow away.

As an example, the Pseudo-NMOS circuit shown in Figure 4 can be made into a dynamic logic structure by adding an evaluation NMOS and connecting it to a clock with the PMOS as shown in Figure 6. During the precharge phase, the output is pulled high through the PMOS in the ON state. When the clock goes high in the evaluation stage, the output will be data-dependent. If the input signals A AND B are high OR if C is high, a path to ground through the evaluation NMOS will be formed and the output node will be pulled low. If these conditions are not met, then the output will remain high. Regardless of the resultant logic level of the output node at the end of the evaluation phase, the output node will be pulled high again when the clock goes low for the next precharge phase.

There are many advantages to using dynamic CMOS logic over static CMOS logic or Pseudo NMOS logic. The elimination of the complimentary PMOS transistors significantly reduces the surface area needed to implement the various logic functions not only because the physical number of transistors is nearly cut in half, but because the physical size of the PMOS transistors tend to be much larger than the size of an NMOS transistor. The switching speeds are also increased using the dynamic logic configuration since the speed bottleneck caused by the lengthier time the PMOS requires to pull-up the output node is eliminated. Since this node is already precharged high through the PMOS during the precharge phase, the output node needs only to be selectively discharged during the evaluation phase. Discharging the output node through the NMOS devices is significantly faster than the time needed to charge up the output node through the PMOS device.

Although increased speed over static or Pseudo NMOS logic is a significant achievement of the dynamic logic, there are several potential problems with the implimentation of this design that need to be considered. Since the basic dynamic CMOS logic configuration causes the output node to be disconnected from VDD during the evaluation phase, even if the output is also disconnected from GND, the charge of the output node will begin to diminish due to the non-ideal effects of the system. Parasitic capacitances, for example, may leak the charge away from the output node and eventually cause a logic error. Since there is, however, a finite time needed for the charge to erroneously escape, the use of faster the clock speeds will eliminate this kind of error. This implies however, that there is a minimum clock speed at which dynamic CMOS logic structures may be operated. It also eliminates the possibility to idle the basic dynamic CMOS logic circuit.

These drawbacks however, are not without a solution. In many cases, the specifications of the system do not require the circuit to ever idle or run at relatively slow clock speeds. In these cases, the fastest clock speed possible is desired, making the minimum clock speed of the dynamic logic configuration a non-issue. In other cases, some of the static benefits can be introduced to the dynamic logic configuration with the addition of a ‘weak’-PMOS device added between the output node and VDD as shown in Figure 7. If the gate is connected to GND, this PMOS device will always be turned ON. Then, even in the evaluation phase, the output node will be connected in some capacity to VDD. This PMOS, the ‘keeper,’ has the effect of maintaining the output node charge even at slower clock speeds. The keeper transistor is designed to be weak enough so that a path to GND through the NMOS logic block during the evaluation phase will significantly overpower the effects of the keeper PMOS and easily pull the output node to GND. Although this configuration has advantages, it does introduce another PMOS device into each stage and also causes excess power dissipation due to possibility of the connection from VDD to GND through the NMOS devices and the PMOS keeper. When such a circumstance occurs, the NMOS and PMOS must ‘fight’ each other to pull-up or pull-down the output through VDD or GND respectively, and power is lost. For high-performance circuits, an alternative is clearly needed.

The use of a keeper PMOS in dynamic logic could be further improved by connecting the gate of the keeper not to GND, but to the output node of the inverter stage as shown in Figure 8. The keeper would now function as a latch cutting off whenever the output of the inverter is high. In this way, power dissipation is significantly reduced whenever a pull-down path to GND has been formed in the NMOS logic block since this would make the input to the inverter low and thus the output of the inverter high. When the output of the inverter is low however, as would be the case if no pull-down path to ground was formed in the NMOS logic block, the keeper PMOS would turn on and maintain the output high charge on the precharge node even at reduced clock speeds or an idle.

Other characteristics of dynamic CMOS logic that must be taken into consideration when designing dynamic logic are the problems that can occur when cascading the dynamic logic blocks. Due to the finite pull down time of the NMOS logic block, during the very first portion of the evaluation phase, the output will always register an output high state for at least a brief moment in time before the output charge can be removed via the pull-down path to GND. This is considered a ‘racing’ problem since the logic is evaluated correctly only when the time to pull down the output node is faster than the time needed for the briefly high output caused by the precharge phase to propagate as an erroneous logic signal to the next stage. Since the output node of one dynamic CMOS logic block is connected to an input of the next dynamic CMOS stage, an output high state however brief could complete a pull-down path to GND in the following stage and erroneously cause a discharge in the output of this next stage. Since the charge on the output node cannot be recovered until the next precharge phase, the logic error would remain and propagate through the system. Dynamic CMOS logic blocks should therefore not be directly cascaded. Note that care must also be taken to insure that the input logic signals to the NMOS logic block are correct and stable for the complete duration of the evaluation stage or a similar logic error could occur.

The errors occurring due to cascaded dynamic logic blocks can be overcome by adding an inverter stage between the output of one stage and the input of another (see Fig. 9).

This inverter then would start out low at the very beginning of the evaluation phase. The output low state of the inverter would cutoff the NMOS logic gates in the next stage preventing any erroneous pull-down path. If a pull-down path is formed by the NMOS logic block of the first stage, the output of the inverter buffer would conditionally charge from low to high. Only if the inputs to the first stage NMOS logic block warrant a discharge of the output node would the output inverter make the low to high transition. When the output of this inverter buffer goes high, the following stage of NMOS logic would conditionally form a pull-down path to ground. In this way, the addition of the inverter buffer eliminates any logic errors caused by the finite pull-down time of the NMOS logic block. This kind of design is referred to as Domino Logic since the pull-down of one stage can conditionally cause the pull-down of succeeding stages and so on like falling dominoes. The number of Domino Logic stages that may be cascaded is limited only by the sum of the total pull-down times in all cascaded logic blocks which must be contained within the evaluation clock phase. Drawbacks to this design are of course the addition of two additional components to each dynamic block. Extra design consideration must also be observed when using dynamic CMOS logic blocks in conjunction with static CMOS logic blocks. Since the final output to the Domino logic blocks is the inverted form of the origonal output due to the additional inverter buffer stage, only non-inverting logic may be used between the output and input of dynamic logic. That is, since the inverter must make only one conditional state change from logic low to high (not high to low) during the evaluation phase only an even number of static logic blocks may be used in between dynamic logic blocks.

An alternative to Domino Logic is NORA or Domino-Zipper Logic. NORA stands for ‘no-race,’ indicating another method to eliminate the ‘racing’ problem of directly cascaded dynamic logic blocks [6]. Figure 10 depicts the basic structure of NORA logic which is characterized by alternating the MOSFETs in the logic block from PMOS to NMOS logic gates and so on. Note that the function of the clocked n- and p- fets

in the PMOS logic stage are reversed compared to the NMOS logic stage. Although this structure eliminates the cascading problem, the excess use of PMOS in forming the logic gates reduces the maximum clocking speed and increases the surface area of the system. For this reason, it is preferable to use only the NMOS for the logic gates and leave the PMOS as precharge elements. Further design considerations for NORA logic are needed when combining the dynamic NORA blocks with static blocks. As observed with Domino Logic, the output may only be allowed to change from low to high once during the evaluation phase of the NMOS logic and visa-versa for the PMOS, so only an even number of static blocks may be used in between two of the dynamic blocks.

Another significant drawback to this configuration is the use of the two-phase clock. For a circuit operating at high speeds, the clock characteristics become increasingly important. The signals of both clock phases must be delivered at nearly the same instant for the circuit to operate correctly. Routing a one phase clock to the millions of circuit elements such that the delay is minimized is a challenging design issue in and of itself. Routing a second clock phase to a similar quantity of circuit elements such that the delay is minimized compared not only to itself, but to the first clock phase becomes a serious problem. The time delay between the first and second clock phase is known as clock skew. The presence of clock skew in a circuit reduces the maximum operation speed of that circuit, since the logic cannot be correctly evaluated during this delay time [8]. Clock skew, as shown in Figure 11, can be eliminated by using only one clock phase, or true single-phase clocking (TSPC), to clock the circuit.

The use of dynamic CMOS logic tends to increase circuit speeds and reduce chip area, while static CMOS is attractive for its robustness and ability to operate at low toggle frequencies. Combining these two logic types can yield a performance improvement in a variety of useful functions such as latches, flipflops, and differential latches. Combining precharged blocks with nonprecharged blocks is referred to as combinational logic. Dynamic Ratio-Insensitive latches can be formed by cross-connecting two clocked full latches as shown in Figure 12 [9]. This configuration inherently provides a differential output with is very useful in forming a logic family. Even though two inputs, the data and its inverse, are needed for this latch, the delays are actually comparable or less than that of nondifferential latches [9]. A high-speed dynamic differential flipflop can be formed by merging these two differential latches by connecting the outputs of a DRIS(P) stage to the inputs of a DRIS(N) stage [9]. By arranging the size of the PMOS transistors in the DRIS(P) stage such that the loading on the nodes is minimized, the flipflop can be made to switch very fast [9]. In this way, dynamic logic can be used to construct a high-speed dynamic flipflop [9].

Another design modification that improves circuit performance is to reduce the number of transistors connected to the clock. At high clock speeds, those transistors connected to the clock must rapidly switch ON and OFF causing dynamic power dissipation. A circuit that has fewer clocked transistors can potentially provide more power savings over a device that has a greater number of clocked transistors. An improvement, therefore, over the differential latch described above is the single-transistor-clocked latch shown in Figure 13 [9]. Using this configuration, only one PMOS is clocked instead of two. Not only are the number of PMOS transistors reduced, but the number of clocked transistors are reduced as well. The latch is, however, subject to the same design conditions as for the basic dynamic CMOS logic structure in that the inputs must be glitch-free for the duration of the evaluation phase and care must be taken when cascading to other dynamic circuit blocks.

While dynamic circuit elements inherently require more design effort to overcome potential conflicts as with slower clock speeds, noisy inputs, and direct cascading, dynamic logic allows for vastly improved clock speeds over standard static CMOS design. For applications which require speeds surpassing the static circuits capabilities, the extra effort associated with designing dynamic logic becomes justifiable. If designed and implemented correctly, dynamic logic offers smaller area and higher speeds than are possible with fully static logic.


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